Power device and Technology;
Process integration;
Power IC design;
Reliability engineering;
Power device modeling; Recent Research Project (Last three years)：
National Key Scientific and Technological Project:
Research on digital auxiliary RF power integration technology
The technology platform of PDP driver IC and device modeling
National Natural Science Foundation of China
Research on hot carrier degradation mechanism and lifetime model of power SOI-LIGBT devices
Study and applications of analysis methods of fast-scale Oscillation in bridge power switching sonverter
Research on the modeling and control methods of SIMO DC-DC converter
Natural Science Foundation of the Jiangsu Province
Mechanism of the reliability of power SOI-IGBT transistor
Reliability of power LDMOS transistor
Power LDMOS dynamics of hot carrier effects and life model
Other projects of the Jiangsu Province
1.Key technology research on single-chip integrated intelligent power module (IPM)
Key technology of a new generation of super-junction power MOS device

11, 2012- present, Distinguished professor of Jiangsu province. The vice dean of Electronic Science and Engineering, Southeast University. IEEE senior member.
4, 2010- 10, 2012, Professor. The vice dean of Electronic Science and Engineering, Southeast University.
9, 2008- 9, 2009, Visiting Scholar at University of California, Irvine.
4, 2007-3, 2010, Associate professor, National ASIC System Engineering Research Center, Southeast University.
4, 2006-3, 2007, Instructor, National ASIC System Engineering Research Center, Southeast University.
4, 2003-3, 2006, Assistant professor, National ASIC System Engineering Research Center, Southeast University.

1.A Novel Compact High-Voltage LDMOS Transistor Model for Circuit Simulation, IEEE Transactions on Electronic Devic,2013, 60（1）, 346-353;
2.Reliability concern on extended E-SOA of SOI power devices with p-sink structure, IEEE Transactions on Device and Materials Reliability,2013, 13（1）, 161-166;
3.Anomalous Hot-carrier-induced Linear Drain Current Degradation of LDMOS under Pulse Gate Stress with different Amplitudes, IEEE Electron Device Letters,2013, 34（6）, 786-788;
4.Reliability Concern and Design for the Lateral Insulator Gate Bipolar Transistor Based on SOI Substrat, Solid-State Electronics,2013,85,28-38;
5.Model of Hot-carrier Degradation for Lateral IGBT Device on SOI Substrate, Electronics Letters,2013, 49（7）, 497 – 499;
6. Linear Drain Current Degradation of ps-LDMOS Transistor under Isubmax and Igmax stress, IEEE Electron Device Letters,2013, 34（8）, 1032-1034;
7. Investigations of hot-carrier-induced degradation for 700V n-LDMOS transistor under different stress conditions, IETE Journal of Research,2013,59,410-414;
8. Analysis of the Electrical Characteristics of 600V-Class Electron Irradiated Fast Recovery Superjunction VDMOS，Solid-State Electronics，2013，80，38-44；
9. High voltage Superjunction VDMOS with low reverse recovery loss, Electronics Letters,2013, 49（3）,219-220;
10. Research of a novel temperature adaptive gate driver for power metal-oxide semiconductor, IET Power Electron.,2013, 1-3;
11. Analytical model for energy recovery circuit of plasma display panel data driver integrated circuit, IET Circuits Devices Syst.,2013,1-7;
12. Power Loss Analysis of Active Clamp Forward Converter in CCM and DCM Operating Modes, IET Power Electron.,2013, 6（6）, 1142-1150;
13. VCCS Models of DPLEDMOS for PDP Data Driver IC, IEICE TRANS. ELECTRON.,2013, E96-C(8), 1061-1068;
14. A Review of Superjunction Vertical Diffused MOSFET，IETE Technical Review，2012，29(1)，44-53；
15. A Novel pLEDMOS Device with Large Current Capability and High Reliability, Semiconductor Science and Technology,2012, 27（10）, 105032 (5pp);
16. The Investigation of Electrothermal Characteristics of High-Voltage Lateral IGBT for ESD Protection, IEEE Transactions on Device and Materials Reliability,2012, 12（1）, 146-151;
17. Hot-carrier Degradation Mechanism for p-type Symmetric LDMOS Transistor with Thick Gate Oxide, Electronics Letters,2012, 48（24）, 1545-1546;
18. A dual-mode single-inductor dual-output dc-dc converter with fast transient response, IEICE electronics express,2012, 9（23）, 1780-1785;
19. Position Sensorless Control of Switched Reluctance Motors Based On Improved BP Neural Network, IET ELECTRIC POWER APPLICATIONS,2012, 6(2), 111-121;
20. Analytical method to optimise turn-on angle and turn-off angle for switched reluctance motor drives, IET ELECTRIC POWER APPLICATIONS,2012, 6（9）, 593-603;
21. Further Notes on the Gaussian Beam Expansion, Chinese Physics Letters,2012, 29（2）, 024301（3pp);
22. A robust 3-D Structure for superjunction VDMOS under UIS condition, IETE Journal of Research,2012, 58（6）, 445-448;
23. Electrical Characteristic Investigation on a Novel Double-Well Isolation Structure in 600-V-Class High-Voltage Integrated Circuits, IEEE Transaction on Electronic Device,2012, 59（12）, 3477-3481;
24. Trench superjunction VDMOS with charge imbalance cells, Solid-State Electronics,2011, 64(1), 14-17;
25. Reliability investigations and improvements of the pLEDMOS for PDP data driver Ics, Semiconductor Science and Technology,2011, 26(5), 055001 (6pp);
26. The optimization of deep trench isolation structure for high voltage devices on SOI substrate, Solid-State Electronics,2011, 63(1), 154-157;
27. Novel hot-carrier degradation mechanisms in the lateral insulated-gate bipolar transistor on SOI substrate, IEEE Transactions on Electron Devices,2011, 58(4), 1158-1163;
28. A novel surface potential-based short channel MOSFET model for circuit simulation, Microelectronics Journal,2011, 42(10), 1169-1175;
29. Threshold voltage degradation under high Vgs and low Vds on 200 v SOI power devices, Microelectronics Journal,2011, 42(5), 609-613;